Apparatus, circuit and method of transmitting signal

ABSTRACT

An apparatus includes a transmission circuit which transmits a data by a differential signal, and a control circuit which halts a portion of the differential signal under a predetermined condition.

This application is based upon and claims the benefit of priority fromJapanese patent application No. 2008-048011, filed on Feb. 28, 2008, thedisclosure of which is incorporated herein in its entirety by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a transmission circuit, and inparticular, to a transmission circuit which outputs a differentialsignal.

2. Description of Related Art

A CML (current mode logic) circuit is generally used as an output bufferof a transmission circuit for a high-speed interface circuits. The CMLcircuit uses a small-amplitude signal level and a differential signaltransmitting method for signal transmission, in order to prevent anattenuation of the signal. Further, the CML circuit is a circuit throughwhich current always passes, resulting in a large amount of currentbeing consumed. Furthermore, in view of the trend for increasing speedof signal transmission, the current consumption of the CML circuitincreases more and more, and becomes a problem.

In Patent Document 1, a technique for decreasing electric powerconsumption of an interface circuit of a transceiver system isdisclosed.

[Patent Document 1] Japanese Unexamined Patent Application PublicationNo. 2004-200990

SUMMARY OF THE INVENTION

According to one exemplary aspect of the present invention, an apparatusincludes a transmission circuit which transmits a data by a differentialsignal, and a control circuit which halts a portion of the differentialsignal under a predetermined condition.

According to another exemplary aspect of the present invention, acircuit includes a transmission circuit which transmits a data by adifferential signal, and a control circuit which halts a portion of thedifferential signal under a predetermined condition.

According to another exemplary aspect of the present invention, a methodincludes transmitting a data by a differential signal, and halting aportion of the differential signal under a predetermined condition.

BRIEF DESCRIPTION OF THE DRAWINGS

Other exemplary aspects and advantages of the invention will be mademore apparent by the following detailed description and the accompanyingdrawings, wherein:

FIG. 1 is an example of a block diagram of the present invention;

FIG. 2A is an example of a waveform of the present invention;

FIG. 2B is another example of a waveform of the present invention;

FIG. 3 is yet another example of a waveform of the present invention;

FIG. 4 is another example of a waveform of the present invention; and

FIG. 5 is yet another example of a waveform of the present invention.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENT

A power consumption increase according to an increase in speed of aninterface is problematic. In a high-speed interface circuit such as aCML circuit, a differential circuit is used for preventing anattenuation of a transmission signal through a transmission path. Atransmission circuit using the differential circuit transmits anormal-phase signal and an opposite-phase signal. Therefore, the numberof output buffers is twice that of a single-phase transmission circuit,and thus, the power consumption is increased.

A transmission circuit which is disclosed in the Patent Document 1 isconfigured as a single-phase transmission circuit. Therefore, when sucha transmission circuit is configured as a differential transmissioncircuit, the increase in power consumption may not be reduced.

In the present invention, by halting a mate signal of the differentialsignal (e.g., the differential signal includes a normal phase signal andan opposite phase signal which is a “mate” to the normal phase signaland vice versa), the power consumption may be reduced.

FIG. 1 shows an example of a block diagram of an interface circuit 100.Interface circuit 100 includes a transmission circuit 101, a receivercircuit 102, and a transmission path 103 connected to the transmissioncircuit 101 and the receiver circuit 102. The transmission circuit 101and the receiver circuit 102 may be installed in different apparatuseswith each other.

The transmission circuit 101 includes a plurality of flip-flops 1 to n,a control circuit 10, buffers 21 and 22, and a switching circuit 30.

The plurality of flip-flops 1 to n operate as a monitor circuit. Theplurality of flip-flops 1 to n (a monitor circuit) are connected inseries to form a shift register 110. Each of the flip-flops 1 to nreceives a clock signal CLK and transfers input data to the nextflip-flop in sync with the clock signal.

Specifically, the flip-flops are connected as follows. Transmission datais inputted to an input terminal of the flip-flop 1, an output terminalof the flip-flop 1 is connected to an input terminal of the flip-flop 2,an output terminal of the flip-flop 2 is connected to an input terminalof the flip-flop 3, . . . , and an output terminal of the flip-flop n−1is connected to an input terminal of the flip-flop n. The flip-flops 1to n−1 output respective output data signals S1 to Sn−1 to thesucceeding flip-flops. The flip-flop n outputs normal-phase andopposite-phase differential signals to the buffers 21 and 22,respectively, in response to an output data signal of the flip-flop n−1.

In other words, the flip-flop n outputs the opposite-phase output datasignal from one output terminal thereof (hereinafter, referred to as an“opposite-phase output terminal”) to the switching circuit 30, andoutputs the normal-phase output data signal from the other outputterminal (hereinafter, referred to as a “normal-phase output terminal”)to the buffer 22.

The switching circuit 30 is connected between the opposite-phase outputterminal of the flip-flop n and an input terminal of the buffer 22. Theswitching circuit 30 is configured by a MOS transistor, for example. Theswitching circuit 30 is turned OFF according to a control signal inputto a gate of the MOS transistor so as to block the opposite-phase outputsignal from the flip-flop n to the buffer 22. Further, the configurationof the switching circuit 30 may be modified as long as the switchingcircuit 30 may switch between ON and OFF according to the controlsignal. For example, the switching circuit 30 may be configured by arelay switch.

The buffer 21 buffers the normal-phase output of the flip-flop n andoutputs the normal-phase output to the transmission path 103 as anormal-phase transmission signal. The buffer 22 buffers theopposite-phase output of the flip-flop n which is passed through theswitching circuit 30, and outputs the opposite-phase output to thetransmission path 103 as an opposite-phase transmission signal.

The control circuit 10 receives the respective output data signals S1 toSn−1 of the flip-flops 1 to n−1, and detects the successiveness oftransmission data values. Then, the control circuit 10 transmits thecontrol signal to the switching circuit 30 according to the detectionresult. For example, if the control circuit 10 detects transmission datavalues which is the same as one another and successive, as like “00 . .. 0” or “11 . . . 1” for example, the control circuit 10 transmits thecontrol signal for turning OFF the switching circuit 30 to the switchingcircuit 30.

In other words, a mate signal of the differential signal is haltedaccording to the control signal. The minimum number of successivetransmission data values which is the same with one another andsuccessive when the control circuit 10 makes the switching circuit 30turned off may be arbitrarily set. For example, when the control circuit10 detects that three transmission data values are the same with oneanother and are successive, such as “000” or “111”, the control circuit10 transmits the control signal for turning OFF the switching circuit 30to the switching circuit 30. In this example, when two transmission datavalues being the same with each other are successive such as “00”, theswitching circuit 30 is maintained at the ON state.

The receiver circuit 102 includes an input differential amplifier 40 andresistor elements R51 and R52. One differential input terminal of thedifferential amplifier 40 receives the output signal of the buffer 21through the transmission path 103, and the other differential inputterminal receives the output signal of the buffer 22 through thetransmission path 103. The resistor element R51 is connected between theone input terminal of the differential amplifier 40 and a supply node ofa voltage Vref. The resistor element R52 is connected between the otherinput terminal of the differential amplifier 40 and the supply node ofthe voltage Vref. The resistor elements R51 and R52 each havesubstantially the same resistance value as the characteristic impedanceof the transmission path 103. Thus, impedance matching of the receivercircuit 102 with the transmission path 103 is accomplished.

An example of an operation of the exemplary embodiment will be describedbelow.

A transmission data is sequentially transmitted to the flip-flop nthrough the flip-flops 1 to n−1. The flip-flop n outputs thedifferential signal. During a normal operation, a normal-phase outputtransmission signal from the output buffer 21 and an opposite-phaseoutput transmission signal from the output buffer 22 are outputted tothe receiver circuit 102 through the transmission path 103.

The control circuit 10 detects the state of the transmission data valuesfrom the output signals S1 to Sn−1 of the flip-flops 1 to n−1. Forexample, if the transmission data is “0101”, the output signalsoutputted from the flip-flop n becomes a waveform as shown in FIG. 2A.

Further, if the transmission data is “010001”, the output waveformsbecome as shown in FIG. 2B, since the transmission data “010001” has asuccessiveness of “000”.

When the transmission data such as “0101”, in which data values “0” and“1” are repeated, is inputted, the waveforms of the output signals fromthe flip-flop n frequently rise and fall. Therefore, the control circuit10 determines that a period of the waveform is short (i.e., thefrequency is high), on the basis of the transmission data detected fromthe respective output signals of the flip-flops 1 to n−1. Further,according to the waveform of the output signals of the flip-flop n, thetransmission signal outputted from the transmission circuit 101 also hasa waveform in which rising and falling frequently occur.

On the other hand, if the transmission data such as “10001”, in which“0” is successively repeated and the number of repetition of data “0”and “1” is small, is inputted, the waveform of the output signals of theflip-flop n rarely repeatedly rise and fall. Therefore, the controlcircuit 10 determines that the period of the waveform is long (thefrequency is low), on the basis of the transmission data detected fromthe respective output signals of the flip-flops 1 to n−1. Further, thelong waveform period may mean that either “0” or “1” is successivelyrepeated twice or more in the transmission data, for example.

According to the values of the transmission data detected from therespective output signals S1 to Sn−1 of the flip-flops 1 to n−1 asdescribed above, the control circuit 10 turns on the switching circuit30 by a control signal when determining that the waveform period of theoutput signals outputted from the flip-flop n is short, and turns offthe switching circuit 30 by the control signal when determining that thewaveform period of the output signals outputted from the flip-flop n islong.

In other words, when the period of the transmission signal is shorterthan a predetermined period, the normal differential signal is outputtedfrom the buffer 21 and 22. Conversely, when the period of thetransmission signal is longer than the predetermined period, the matesignal of the differential signal is halted. When the period of thetransmission signal is longer than the predetermined period, the matesignal of the differential signal is transmitted only from the buffer21.

FIG. 3 shows an example of the waveform of output transmission signalsoutputted from the transmission circuit 101 according to the exemplaryembodiment. A term A is a transmission term of the normal differentialsignal in which the switching circuit 30 is turned ON, and a term B is atransmission term of a single phase signal (i.e., the mate signal of thedifferential signal) in which the switching circuit 30 is turned OFF.Further, FIG. 4 shows the waveform of output transmission signals of atransmission circuit including a differential circuit according to therelated art, for comparison. Furthermore, the transmission signals shownin FIGS. 3 and 4 are waveforms which are outputted when the values ofthe transmission data are “1010 . . . 010”, for example.

In both of the terms A of FIGS. 3 and 4, the signal transmission ofnormal differential signals is performed. In the term B of FIG. 3, sincethe switching circuit 30 blocks input of the opposite-phase signal tothe buffer 22, the signal amplitude of the opposite-phase signal doesnot occur. In other words, the buffer 22 does not operate and thus doesnot consume the power consumption. However, in the transmission circuitincluding the differential circuit according to the related art of FIG.4, the normal differential transmission signal is always outputted. Inother words, the buffer circuit always operates even in (during) theterm B.

The term B of FIG. 3 shows the signal transmission of a single phasesignal when the normal-phase transmission signal is at a low level(transmission data is “0”), and a similar operation may be performedeven when the normal-phase transmission signal is at a high level(transmission data is “1”), as shown in FIG. 5.

As described above, the transmission circuit according to the exemplaryembodiment functions as a differential circuit when the transmissionsignals are high-speed signals in which variation such as rising andfalling frequently occurs in the waveforms thereof (the period thereofis short), so as to make high-speed data transmission possible, andblocks the opposite-phase signal when the transmission signals arelow-speed signals in which variation rarely occurs in the waveformsthereof (the period thereof is long). In this way, the transmissioncircuit according to the exemplary embodiment stops the operation of thebuffer which buffers the mate signal of the differential signal in thecase of a low-speed signal in which variation such as rising and fallingrarely occur in the waveform thereof (the period thereof is long), whichmakes it possible to reduce the power consumption of the transmissioncircuit.

Further, the present invention is not limited to the above-mentionedembodiment but may be arbitrarily modified. For example, in theabove-mentioned embodiment, the switching circuit is disposed on theside of the opposite-phase output signal. However, the switching circuitmay be disposed on the side of the normal-phase output signal. Further,the buffer 22 may include the switching circuit 30 inside thereof sothat, even when signals from the flip-flop n are input in the term B ofFIG. 3, a signal from the flip-flop n is blocked by the switchingcircuit 30 within the buffer 22.

Furthermore, in the above-mentioned embodiment, the shift register 110functions as a monitor circuit which informs the control circuit 10 ofsignal variation of the transmission data by the output signals from theindividual flip-flops. The shift register 110 may have a structuredifferent from that in the above-mentioned embodiment so long as it hasfunctions to monitor the successiveness of the values of thetransmission data and to output, to the control circuit 10, informationon whether the same values are successive.

For example, the shift register may have a counter for counting a clocksignal and a comparator for determining whether the transmission datahave either “0” (the signal level thereof is low) or “1” (the signallevel thereof is high), and may output, to the control circuit 10,information on whether “0” or “1” is successively repeated in apredetermined count period. In this case, it is not required to formplural flip-flops, unlike the shift register in the above-mentionedexemplary embodiment.

Further, it is noted that Applicant's intent is to encompass equivalentsof all claim elements, even if amended later during prosecution.

1. An apparatus, comprising: a transmission circuit which transmits adata by a differential signal; and a control circuit which halts aportion of the differential signal under a predetermined condition. 2.The apparatus according to claim 1, wherein the control circuit haltsthe portion of the differential signal while the differential signalbecomes a period longer than a predetermined period.
 3. The apparatusaccording to claim 1, wherein the control circuit halts the portion ofthe differential signal while the data comprises successive same values.4. The apparatus according to claim 1, further comprising: a switchingcircuit which is connected to a transmission path of the portion of thedifferential signal, wherein the control circuit halts the portion ofthe differential signal by switching off the switching circuit.
 5. Theapparatus according to claim 1, wherein the transmission circuitcomprises: a plurality of sequential circuits having a seriesconnection, wherein the data passes through the sequential circuits, andwherein the control circuit receives output signals of each of thesequential circuits, and determines whether the differential signal isunder the predetermined condition, according to the output signals. 6.The apparatus according to claim 1, wherein the control circuit haltsthe portion of the differential signal while the differential signalbecomes a period longer than a predetermined period, wherein thetransmission circuit comprises: a plurality of sequential circuitshaving a series connection, wherein the data passes through thesequential circuits, and wherein the control circuit receives outputsignals of each of the sequential circuits, and determines that thedifferential signal becomes the period longer than the predeterminedperiod when the control circuit receives the output signals havingsuccessive same values.
 7. The apparatus according to claim 1, whereinthe transmission circuit comprises: a plurality of sequential circuitshaving a series connection, wherein the data passes through thesequential circuits, and wherein the control circuit receives outputsignals of each of the sequential circuits, and halts the portion of thedifferential signal while the output signals comprise successive samevalues.
 8. A circuit, comprising: a transmission circuit which transmitsa data by a differential signal; and a control circuit which halts aportion of the differential signal under a predetermined condition.
 9. Amethod, comprising: transmitting a data by a differential signal; andhalting a portion of the differential signal under a predeterminedcondition.
 10. The method according to claim 9, further comprising:halting the portion of the differential signal while the differentialsignal becomes a period longer than a predetermined period.
 11. Themethod according to claim 9, further comprising: halting the portion ofthe differential signal while the data comprises successive same values.12. The method according to claim 9, further comprising: turning off aswitching circuit, which is connected to a transmission path of theportion of the differential signal, for halting the portion of thedifferential signal.
 13. The method according to claim 9, furthercomprising: transmitting the differential signal by a transmissioncircuit which comprises a plurality of sequential circuits having aseries connection, the data passing through the sequential circuits;receiving output signals of each of the sequential circuits; anddetermining whether the differential signal is under the predeterminedcondition according to the output signals.
 14. The method according toclaim 9, further comprising: transmitting the differential signal by atransmission circuit which comprises a plurality of sequential circuitshaving a series connection, the data passing through the sequentialcircuits; receiving output signals of each of the sequential circuits;determining that the differential signal becomes a period longer than apredetermined period when the control circuit receives the outputsignals having successive same values; and halting the portion of thedifferential signal while the differential signal becomes the periodlonger than the predetermined period.
 15. The method according to claim9, further comprising: transmitting the differential signal by atransmission circuit which comprises a plurality of sequential circuitshaving a series connection, the data passing through the sequentialcircuits; receiving output signals of each of the sequential circuits;and halting the portion of the differential signal while the outputsignals comprise successive same values.